High performance tapered varactor

ABSTRACT

Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention generally relates to semiconductor devices and to methodsof fabricating semiconductor devices. More specifically, the inventionrelates to the formation of a high performance varactor on silicon inthe manufacture of integrated circuit devices.

2. Background Art

Varactors are voltage variable capacitors. These devices are essentialfor the design of key radio frequency (RF) CMOS and BiCMOS circuits, andare specifically used as tuning elements in voltage controlledoscillators (VCCs), phase shifters, phase-locked loop (PLL) circuits,and frequency multipliers.

In general, varactor designs must maximize a number of properties. Oneis “tunability,” which is the ratio between the highest and lowestcapacitive values (Cmax/Cmin) over the range of applied voltages for thecircuit. Another is “linearity.” There are two definitions of‘linearity’: 1/sqrt(C) and d(LnC)/dV, where C is the voltage-dependentvaractor capacitance. In the first case it is desired that 1/sqrt(C) bea straight line, and in the second, that d(LnC)/dV be a constant, bothas V varies. Yet another property is “Q,” or quality factor, which afunction of the series resistance of the diode and the capacitive valueof the varactor at the higher frequency ranges of the circuit.

In order to enhance the capacitive swing of a varactor, it also known tovary the dopant concentration of one or both of the diffused electrodesof the diode such that the diffusion has a retrograde dopant profile(that is, the dopant concentration is higher at the lower portion of thediffusion region than it is in the top). These so-called “hyperabrupt”junctions greatly increase the change in varactor capacitance for agiven voltage swing.

In practice, it has proven to be difficult to simultaneously enhancetunability, linearity, and Q of a varactor when integrated into a CMOSor BiCMOS process. For example, considering the PFET source/drainjunction and well as a varactor device, additional n-well implants willdecrease the well resistance and increase varactor Q, but will decreasevaractor tuning range by making the source/drain p-n junction depletionregions smaller.

Accordingly, a need has developed in the art for a varactor design thatoptimizes the tradeoffs between all of these properties, particularlywhen integrated into a process for forming other integrated circuitdevices.

SUMMARY OF THE INVENTION

An object of this invention is to improve varactors in integratedcircuit devices.

Another object of the present invention is to provide a varactor havingimproved Cmax/Cmin with low series resistance.

A further object of the invention is to use FinFET technology to providea varactor having improved Cmax/Cmin and low series resistance.

These and other objectives are attained with a semiconductor structure,which includes a non-planar varactor having a geometrically designeddepletion zone with a taper, as to provide improved Cmax/Cmin with lowseries resistance. Preferably, this depletion zone includes a narrowerportion and a wider portion. Because of the taper, the narrowest portionof the depletion zone can be designed to be fully depleted, while theremainder of the depletion zone is only partially depleted. This resultsin low resistance to a contact at the end of the depletion zone. As thevoltage of a gate of the varactor is moved further into depletion, thefully depleted portion of the depletion zone advances, decreasing theeffective area of the capacitor.

The fabrication of the semiconductor structure may follow that ofstandard FinFET process, with a few additional or different steps. Theseadditional or different steps may include formation of a dopedtrapezoidal (or triangular) shaped silicon mesa, growing/depositing agate dielectric, forming a gate electrode over a portion of the mesa,and forming a highly doped contact region in the mesa where it is notcovered by the gate electrode.

Further benefits and advantages of the invention will become apparentfrom a consideration of the following detailed description, given withreference to the accompanying drawings, which specify and show preferredembodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view showing a varactor embodying the present invention.

FIG. 2 is a side view taken along line A-A′ of FIG. 1.

FIG. 3 is a side view taken along line B-B′ of FIG. 1.

FIG. 4 shows a varactor embodying this invention and having acharge-neutral n-well of a given size.

FIG. 5 shows the varactor of FIG. 4 with a smaller charge-neutraln-well.

FIG. 5A shows a varactor embodying the present invention and with acurved surface.

FIG. 6 illustrates a substrate structure that may be used in thefabrication of the varactor of FIGS. 1-5.

FIG. 7 depicts two hardmask films formed on the substrate of FIG. 6.

FIG. 8 shows a pattern etched into the structure depicted in FIG. 7.

FIG. 9 illustrates a doping process that is used in the preferredprocedure for fabricating the varactor of FIGS. 1-5.

FIG. 10 represents the step of growing and then removing a sacrificiallayer in the varactor fabrication process.

FIG. 11 shows the formation of a gate dielectric in the varactorfabrication process.

FIG. 12 depicts a gate electrode formed in the varactor fabricationprocess.

FIG. 13 shows the gate electrode of FIG. 12 after being patterned andetched.

FIG. 14 illustrates a sidewall grown on the gate electrode.

FIG. 15 shows spacers deposited on the gate electrodes depicted in FIG.14.

FIG. 16 illustrates an ion implantation step in the fabrication of thevaractor of FIGS. 1-5.

FIG. 17 depicts a dielectric formed on the structure of FIG. 16.

FIG. 18 shows contact vias formed in the dielectric of FIG. 17.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1-5 illustrate semiconductor structure 10 including varactor 12.More specifically, structure 10 includes hardmask 60, mesa 16, gatedielectric 20, contact or contact region 22, gate electrode 14, contacts26 and isolation region 30. With particular reference to FIGS. 4 and 5,mesa 16 includes charge neutral region 32 and depletion region 34, andthis depletion region includes partially and fully depleted portions 36and 40.

As viewed in FIG. 1, mesa 16 has a downwardly inwardly tapered shape;and with the embodiment of the invention illustrated in FIGS. 1-5, themesa has a trapezoidal cross-sectional shape. The mesa may have othershapes, though, such as a triangular shape, or other shapes. Forinstance, as shown in FIG. 5A, the mesa may have surfaces to enablecustomized capacitance vs. voltage behavior. Charge neutral region 32,with the embodiment of the invention shown in FIGS. 1-5, has atriangular cross-sectional shape; and, as viewed in FIG. 1, region 32extends, downward from the top of the mesa 16, along a central axisthereof. Depletion region 34 is located outside of charge-neutral region32 and fills the portion of the mesa 16 outside of that charge-neutralregion.

Because of the taper of mesa 16, the narrowest region of the mesa can befully depleted while the remainder of the mesa is only partiallydepleted. This results in low resistance to the contact 22 at the end ofthe mesa. As the voltage of the gate 14 is moved further into depletion,the depletion region 40 advances, decreasing the effective area of thecapacitor as well as increasing the thickness of the space-charge region36. With particular reference to FIGS. 4 and 5, as the voltage Vgs ofpolysilicon gate 14 changes from accumulation to depletion range, thesize of charge-neutral region 32 shrinks.

The fabrication of structure 10, described in detail below, may followthat of standard FinFET process, with a few additional or differentsteps. These additional or different steps may include formation of adoped trapezoidal (or triangular) shaped silicon mesa 16, with hardmask24 disposed above said mesa, growing/depositing a gate dielectric 20,forming a gate electrode 14 over a portion of the mesa, and forming ahighly doped contact region 22 in the mesa where it is not covered bythe gate electrode.

FIGS. 6-18 illustrate the fabrication of structure 10 in more detail.

FIG. 6 shows a substrate 50 comprised of a bottom layer 52, an isolationlayer 54 formed on top of the bottom layer, and an active semiconductorlayer 56 formed on top of the isolation layer.

Preferably, substrate 50 is a silicon-on-insulator (SOI) substrate,wherein an upper layer of silicon is separated from the bulk substrateby a buried oxide layer (BOX). Alternatively, the isolation layer couldbe SiGe. Other types of substrates can be used, and, for instance, thesubstrate can be a bulk substrate made of single-crystal silicon, orcould also be other semiconductor materials such as SiGe and a GroupIII-V semiconductor such as GaAs or InP. Moreover, the upper surface ofthe substrate could be doped with an atom that increases strain andhence mobility of minority carriers. For a silicon substrate, a Geimplant may be used to achieve this result.

With reference to FIG. 7, hardmask films 60 and 62 are formed onsubstrate 50. For example, film 60 may be made by thermal oxidation ofsilicon to form SiO2, 5 nm to 40 nm thick. Film 62 may be Si3N4, 2 nm to7 nm thick, and formed by a chemical vapor deposition (CVD) process.Other suitable materials, such as silicon oxynitride, and other suitableprocedures may be used to form hardmask films 60 and 62. In analternative embodiment, the films 60 and/or 62 may be formed at agreater thickness in regions were the inventive varactor is to beformed, than in regions where a FinFET is to be formed. This may beaccomplished by ordinary means of masking and etching/depositingdiffering thicknesses of SiO2 and Si3N4 in the varactor and FinFETregions.

With reference to FIG. 8, the next step in the fabrication process is topattern and etch the hardmask films and active silicon 56, stopping theetch on isolation layer 54, and forming varactor pre-structure 66 andfin 70. Any suitable etching procedure may be used to etch the hardmaskfilms and the silicon layer. As represented in FIG. 8, some, or all ofthe hardmask material may be etched away during, or after activesemiconductor etching. Optionally, the hardmask may be selectivelythinned, or removed, using a mask, opened on fin 70. This latter optionmay be used if a Tri-gate structure is to be formed from the fin.

As illustrated in FIG. 9, the varactor pre-structure 66 is thenselectively doped with mask and ion implant. For example, As or P dopingmay be used to achieve between 10¹⁵ to 5×10¹⁸ cm³. Alternatively, thevaractor pre-structure could be p-doped using, for example, Boron. Thedopant can, for example, be at a dose of between approximately 10¹¹ to10¹⁴ atoms/cm² and at an energy between approximately 10-40 keV. In analternate embodiment, this ion implant would be replaced or supplementedby ion implants with the same mask but tilted at angles so as to enterthe exposed sidewalls of the varactor mesa 56. In this case, the energyof the implant may be chosen so as to avoid penetration of the hardmask60 and provide further customization of the capacitance-voltagecharacteristic.

At this point, and with reference to FIG. 10, a sacrificial oxidationprocess may be used to repair any damage to surfaces of varactorpre-structure 66 and fin structure 70 during the etch process. Ifdesired, oxidation may also be used to reduce the widths of structures66 and 70, allowing desired dimensions to be achieved. For example,sacrificial layers 72 1-3 nm thick may be grown on structures 66 and 70.These layers may then be removed, for instance, via an isotropic etch(BHF/HF) to expose clean, smooth surfaces.

Next, as illustrated in FIG. 11, gate dielectrics 74 are grown ordeposited on structures 66 and 70. These dielectrics 74 may be thermallygrown silicon oxide or deposited silicon oxide, silicon oxynitride, orother high dielectric constant material that is suitable for use as agate dielectric.

With reference to FIG. 12, gate electrode 76 is then formed overstructures 66 and 70. Any suitable materials may be used to form thegates; and, for instance, gate electrode 76 may be doped polysilicon orother conductors such as tungsten, or metal silicide. Silicon germanium,a refractory metal or compounds such as titanium nitride or molybdenummay also be used. Also, optionally, the gate electrode may be planarizedby a chemical-mechanical polish (CMP) or a reactive ion etch (RIE) back.

With reference to FIG. 13, the next step in the fabrication is topattern and etch the gate electrode 76, forming gates 80 and 82. To dothis, a gate mask (not shown) is defined and then the underlying gatematerial 76 is etched to form gates 80 and 82, with the etching stoppingon the gate oxide and the insulator layer 54. Gate 80 is electricallyinsulated from varactor structure 66 by the gate oxide and the hard maskoverlying the varactor structure; and, likewise, gate 82 is electricallyinsulated from the fin structure 70 by the gate oxide and the hard mask.After formation of gates 80 and 82, the gate mask can be removed.

Next, as illustrated in FIG. 14, 1-3 nm layers 84 of SiO2 are grown onthe sidewalls of gates 80 and 82 using an oxidation process. At thispoint, an ion implant of appropriate dopants may be used to form dopedsource and drain extensions and halos into FinFET. These ions mayoptionally also be implanted into exposed portions of varactor activesilicon 66.

The next step in the process, with reference to FIG. 15, is to formspacers 86 on the sidewalls of structures 66 and 70. This can be done bydeposition and selective etching of a dielectric such as silicon nitrideor silicon dioxide. This spacer etch may also be used to remove sidewalloxide that was on top of the gate electrodes, as shown in FIG. 15.

After spacer formation, and with reference now to FIG. 16, doping of thesource and drain regions of the FinFET 70 and of the varactor 66 isperformed to make these regions electrically conductive. For example, N+ion implant source/drain into exposed active semiconductor, for alln-type FinFETs and for the varactor. Alternatively, if the varactor bodywas doped p-type (Boron), then this ion implantation must be also p-type(and if the optional extension implant was performed after sidewalloxidation, that too must be p-type for the varactor). This p-typeimplant set could also be used in p-type FinFET source/drain regions.

Doping may be accomplished by ion implantation, gas immersion laserdoping, ion shower doping, solid or gas source diffusion, or otherconventional means. The dopant species is chosen to achieve the requireddevice characteristics, either N-type or P-type, including dopantconcentrations. Angled shallow ion implantation may be used to dope thesides and top of the source and drain regions without completelyamorphizing them, as could result with a deeper vertical ion implant.Any implant damage or amorphization can be annealed through subsequentexposure to elevated temperatures.

As illustrated in FIG. 17, dielectric 90 is formed. This dielectric, forexample, may be silicon dioxide deposited by a CVD process. Othermaterials and other processes may be used, however, to form thedielectric.

After dielectric 90 is formed, vias, shown at 92 in FIG. 18, are formedto contact gates and source/drain regions. Contacts 26 may then beprovided, forming the varactor structure illustrated in FIGS. 1-5.

While it is apparent that the invention herein disclosed is wellcalculated to fulfill the objects stated above, it will be appreciatedthat numerous modifications and embodiments may be devised by thoseskilled in the art and it is intended that the appended claims cover allsuch modifications and embodiments as fall within the true spirit andscope of the present invention.

1. A semiconductor structure, which includes a non-planar varactorhaving a geometrically designed depletion zone with a taper, as toprovide improved Cmax/Cmin with low series resistance.
 2. Asemiconductor structure according to claim 1, wherein said depletionzone includes a narrower portion and a wider portion, and wherein saidnarrower portion is fully depleted and said wider portion is onlypartially depleted.
 3. A semiconductor structure according to claim 1,wherein the varactor further includes a charge-neutral region, and thedepletion zone extends around said charge-neutral region.
 4. Asemiconductor structure according to claim 3, wherein the size of thecharge-neutral region changes in response to changes in a voltageapplied to the varactor.
 5. A semiconductor structure according to claim1, wherein the varactor includes a doped, shaped mesa.
 6. Asemiconductor structure according to claim 5, wherein said mesa furthercomprises a highly doped region.
 7. A semiconductor structure accordingto claim 5, wherein said mesa has a trapezoidal or a triangular shapedcross-section.
 8. A semiconductor structure according to claim 1,wherein the varactor further includes a gate material extending aroundsaid depletion zone.
 9. A semiconductor structure according to claim 8,wherein the varactor further includes a gate dielectric separating saiddepletion zone from said gate material.
 10. A method of fabricating asemiconductor structure, comprising the steps of: providing a substrate;and forming on or above the substrate a non-planar varactor having ageometrically designed depletion zone with a taper, so as to provideimproved Cmax/Cmin with low series resistance.
 11. A method according toclaim 10, wherein the forming step includes the step of providing saiddepletion zone with a narrower portion and a wider portion, and whereinsaid narrower portion is fully depleted while said wider portion is onlypartially depleted.
 12. A method according to claim 11, wherein the sizeof said fully depleted portion varies as a function of a voltage appliedto the varactor.
 13. A method according to claim 10, wherein the formingstep includes the step of providing the varactor with a charge-neutralregion, with said depletion zone extending around said charge-neutralregion.
 14. A method according to claim 10, wherein the forming stepincludes the step of providing the varactor with a doped, shaped mesa.15. A method according to claim 14, wherein said mesa has a trapezoidalshaped cross-section.
 16. A method according to claim 15, wherein saidmesa has a triangular shaped cross-section.
 17. A method according toclaim 10, wherein the forming step includes the steps of forming a gatematerial extending around said depletion zone; and forming a gatedielectric material separating the depletion zone from said gatematerial.
 18. A method of customizing capacitance vs. voltage behaviorof a varactor in a semiconductor structure, the method comprising thesteps of: forming the varactor in the semiconductor structure; andproviding the varactor with an outside surface having a predeterminedcurved shape, as to provide the varactor with a predeterminedcapacitance vs. voltage behavior.
 19. A method according to claim 18,wherein the varactor defines an axis, and the providing step includesthe step of curving said outside surface downwardly inwardly along saidaxis.
 20. A method according to claim 19, wherein the varactor includes:a narrower, fully depleted portion; and a wider, only partially depletedportion.